Selection of Hardware and Development Tools
In this second article of the series, I will begin with the first steps in developing a RISC-V 32I-based microcontroller. For this, I have decided to use a Tang Nano 20K as the implementation platform. However, depending on resource usage, I might consider switching to a Tang Nano 9K if it meets the design requirements.
Since the selected FPGA belongs to the Tang Nano family, this limits the development environment to compatible tools. In this case, I will use Gowin EDA, Gowin’s official software for hardware design and synthesis. Although there are open-source alternatives for loading the bitstream1, such as openFPGALoader, I will initially work with the official tools to ensure compatibility.
Microcontroller Architecture
The processor will implement the RISC-V 32I instruction set, meaning it will feature 32 general-purpose registers2, as defined by the architecture specification. These registers are fundamental in any RISC-V 32I processor, and in this case, besides the basic registers, I will consider adding additional registers for peripheral management, especially for GPIO handling.
Initial Design Components:
- Processing Unit (CPU): Implemented in Verilog.
- Memory: Internal FPGA RAM will be used, and if necessary, external memory.
- GPIO Interface: A basic communication interface with external peripherals.
- Development Tools: Use of Gowin EDA and simulators like Icarus Verilog.
In the upcoming articles, I will develop the processor design and control modules, as well as detail the workflow for programming and testing the FPGA.