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      <title>Design of a RISC-V Microprocessor with GPIO Integration</title>
      <link>http://fabianalvarez.dev/tutorials/riscvduino/idea/</link>
      <pubDate>Tue, 18 Feb 2025 00:00:00 +0000</pubDate>
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      <description>This series documents my attempt to recreate a RISC-V-based microprocessor I previously developed, this time with GPIO integration to expand its functionality.</description>
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      <title>First Steps in RISC-V Microcontroller Development</title>
      <link>http://fabianalvarez.dev/tutorials/riscvduino/primeros_pasos/</link>
      <pubDate>Wed, 19 Feb 2025 00:00:00 +0000</pubDate>
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      <description>This second article in the series documents the selection of hardware and development tools for implementing a RISC-V microcontroller with GPIO integration.</description>
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      <title>Implementing a Register File for a RISC-V 32I Processor on FPGA</title>
      <link>http://fabianalvarez.dev/tutorials/riscvduino/banco_de_registros/</link>
      <pubDate>Sun, 16 Mar 2025 00:00:00 +0000</pubDate>
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      <description>This article explains the importance of the register file in a RISC-V 32I processor and how to implement it in Verilog for an FPGA.</description>
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      <title>Implementing the Control Unit of a RISC-V 32I Processor on FPGA</title>
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      <pubDate>Sun, 16 Mar 2025 00:00:00 +0000</pubDate>
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      <description>In this article, we explain what the Control Unit of a RISC-V 32I processor is and how to implement it step-by-step in Verilog on an FPGA.</description>
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