Tang Nano 9K

If you’ve ever tried to build a microprocessor from scratch, you know it’s a battlefield full of hazards, memory control, and instruction handling. A true digital mess. In the middle of that chaos, I came across a tool that completely changed the way I see FPGA development: LiteX. What is LiteX? LiteX is a framework for designing SoCs (System on Chip) on FPGA, transforming the process into something like assembling LEGO blocks: you pick a processor, add controllers, memory, peripherals, and done!...

Introduction to RISC-V and the 32I Instruction Set RISC-V is an open and free instruction set architecture (ISA) that has gained significant popularity in microprocessor design due to its flexibility and efficiency. Unlike proprietary architectures, RISC-V allows developers and researchers to create custom processors without licensing restrictions. What is RISC-V? RISC-V is an architecture based on the Reduced Instruction Set Computing (RISC) principle, meaning it uses a simplified instruction set to improve hardware efficiency....

HDMI output on FPGA platforms is a powerful way to generate real-time graphics directly from custom hardware. In this article, we’ll explore how to implement HDMI output using the LiteX framework on the Tang Nano 9K, a low-cost FPGA with impressive versatility. I’ve already written a guide on how to get started with LiteX and build a basic SoC in the previous post. 🧱 HDMI Architecture in LiteX By default, the tangnano9k....

Selection of Hardware and Development Tools In this second article of the series, I will begin with the first steps in developing a RISC-V 32I-based microcontroller. For this, I have decided to use a Tang Nano 20K as the implementation platform. However, depending on resource usage, I might consider switching to a Tang Nano 9K if it meets the design requirements. Since the selected FPGA belongs to the Tang Nano family, this limits the development environment to compatible tools....

Implementing a Register File for a RISC-V 32I Processor on FPGA This article is part of our series on designing and implementing a RISC-V 32I processor on the Tang Nano 20K FPGA. Today we’ll dive into an essential component of any processor: the register file. We’ll explore what it is, why it’s critical to RISC-V architecture, and how to efficiently implement it in Verilog. Additionally, we’ll discuss key optimizations to ensure robustness and compatibility with real hardware....