A Novel Approach to RISC-V Implementation on FPGAs
Introduction The RISC-V instruction set architecture has gained significant traction in recent years due to its open-source nature and flexibility. This paper explores novel implementation strategies for RISC-V processors on FPGA platforms. Related Work Previous implementations of RISC-V on FPGAs have focused primarily on… Methodology Our approach consists of three main components: Optimized Register File: We redesigned the register bank to reduce latency Efficient Control Unit: A new FSM-based control unit Pipeline Optimization: Careful balancing of pipeline stages Register File Design The register file implementation uses dual-port memory…...